IC 74173 DATASHEET PDF

datasheet, circuit, data sheet: HITACHI – 4-bit D-type site for Electronic Components and Semiconductors, integrated circuits, diodes. datasheet, pdf, data sheet, datasheet, data sheet, pdf, Hitachi Semiconductor, 4-bit D-type Register (with 3-state Outputs). Quad D-type flip-flop; positive-edge trigger; 3-state. PDF datasheet. OE1, 1 •, 16, Vcc. OE2, 2, 15, MR. Q0, 3, 14, D0. Q1, 4, 13, D1. Q2, 5, 12, D2.

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During normal operation of the device, the outputs of the D flip—flops appear at these pins. When either M or N or both is are high the output is disabled to the high-impedance state; however sequential operation of the flip-flops is not affected.

The 3-state outputs allow the device to be used in bus organized systems.

NTE – IC-TTL Quad D Flip-Flop w/Three-State Outputs

Enable Controls are low, data at the D inputs are loaded into. When either or both of the. Output Enable Controls are high, the Q outputs of the device. Clearing is enabled by taking the clear input to a logic high level. Home – IC Supply – Link.

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The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. During normal operation of the. The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level.

When either M or N or both is are high the output is disabled to the high-impedance state. If either of the 2 input disables are taken to a logic high level, the Q outputs are fed datashdet to the inputs. Data on these pins, when enabled by the.

74173 PDF Datasheet浏览和下载

A high level on this pin resets all flip—flops and forces the Q outputs low, if they are not already in high—impedance state. Home – IC Supply kc Link. When either or both of the Output Enable Controls are high, the Q outputs of the device are in the high—impedance state. When both Data Enable Controls dztasheet low, data at the D inputs are loaded into the flip—flops with the rising edge of the Clock input.

Data—Enable Controls, are entered into the flip—flops on the. If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. The four D type Flip-Flops operate synchronously from a common clock. When either or both of these controls are high, there is no change in the state of the flip—flops, regardless of any changes at the D or Clock inputs.

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(PDF) 74173 Datasheet download

Clearing is enabled by taking the clear input to a logic. Data on these pins, when enabled by the Data—Enable Controls, are entered into the flip—flops on the rising edge of the clock. The 3-state outputs allow the. Output Enable Control daatsheet. The data outputs change state on the positive going edge of the clock.

Datasheet(PDF) – Hitachi Semiconductor

A high level on this pin resets all. Active—low Data Enable Control inputs. When both controls are. When both controls are low, the device outputs display the data in the flip—flops. The outputs are placed in the 3-stage mode when either of the.

During 3—state operation, these outputs assume a high— impedance state. During 3—state operation, these outputs assume a high—.