In this module we will study automatic test pattern generation (ATPG) using sensitization–propagation -justification approach. We will first introduce the basics of. 1. VLSI Design Verification and Testing. Combinational ATPG Basics. Mohammad Tehranipoor. Electrical and Computer Engineering. University of Connecticut. Boolean level. • Classical ATPG algorithms reach their limits. ➢ There is a need for more efficient ATPG tools! 6. Circuits. • Basic gates. – AND, OR, EXOR, NOT.

Author: Malagore Kagasho
Country: Oman
Language: English (Spanish)
Genre: Health and Food
Published (Last): 6 March 2015
Pages: 320
PDF File Size: 1.48 Mb
ePub File Size: 3.63 Mb
ISBN: 860-1-93349-306-8
Downloads: 63057
Price: Free* [*Free Regsitration Required]
Uploader: Mezir

Equivalent faults produce the same faulty behavior for all input patterns.

If one driver dominates the other driver in a bridging situation, the dominant driver forces the logic to the other one, in such case a dominant bridging fault is used. Sequential-circuit ATPG searches for a sequence of test vectors to detect a particular fault through the space of all possible test vector sequences. This page was last edited on 23 Novemberat For designs that are sensitive to area or performance overhead, the solution of using sequential-circuit ATPG and partial scan offers an attractive alternative to the popular full-scan solution, which is based on combinational-circuit ATPG.

In stuck-short, a transistor behaves as it is always conducts or stuck-onand stuck-open is when a transistor never conducts current or stuck-off. Fault propagation moves the resulting signal value, or fault effect, forward by sensitizing a path from the fault site to a primary output.

It is also called a permanent fault model because the faulty effect is assumed to be permanent, in contrast to intermittent faults which occur seemingly at baiscs and transient faults which occur sporadically, perhaps depending on operating conditions e.

Views Read Edit View history. For nanometer technology, many current design validation problems are becoming manufacturing test problems as well, so new fault-modeling and ATPG techniques will be needed. This model is used to describe faults for CMOS logic gates.


Various search strategies and heuristics have been devised to find a shorter sequence, or to find a sequence faster. During design validation, engineers can no longer ignore the effects of crosstalk and power supply noise on reliability and performance. These metrics generally indicate test quality higher aatpg more fault detections and test application time higher with more patterns.

Bridging to VDD or Vss is equivalent to stuck at fault model. Second, it is possible that a detection pattern exists, but the algorithm cannot find one.

The generated patterns are used to test semiconductor devices after manufacture, or to assist with determining the cause of failure failure analysis [1]. In the past several decades, the most popular fault model used in practice is the single stuck-at fault model. The effectiveness of ATPG is measured by the number of modeled defects, or fault modelsdetectable and by the number of generated patterns.

In the latter case, dominant driver keeps its value, while the other one gets the AND or OR value of its own and the dominant driver. However, according to reported results, no single strategy or heuristic out-performs others for all applications or circuits.

The output of a test pattern, when testing a fault-free device that works exactly as designed, is called the expected output of that test pattern.

NPTEL :: Computer Science and Engineering – VLSI Design Verification and Test

The ATPG atph for a targeted fault consists of two phases: ATPG is a topic that is covered by several conferences throughout the year. From Wikipedia, the free encyclopedia. In such a circuit, any single fault will be inherently undetectable. Hence, if a circuit has n signal lines, there are potentially 2n stuck-at faults defined on the circuit, of which some can be viewed as being equivalent to others.

  ASCE 59-11 PDF

Also, due to the presence of memory elements, the controllability and observability of the internal signals in basids sequential circuit are in general much more difficult than those in a combinational logic circuit.

Combinational ATPG Basics

First, the fault may be intrinsically undetectable, such that no patterns exist that can detect that particular fault. Therefore, many different ATPG methods have been developed to address combinational and sequential circuits.

As apg trends move toward nanometer technology, new manufacture testing problems are emerging. A fault is said to be detected by a test pattern if the output of that test pattern, when testing a device that has only that one fault, is different than the expected output.

At transistor level, a transistor maybe atlg or stuck-open. The single stuck-at fault model is basicx because it is defined based on a structural gate-level circuit model. The logic values observed at the device’s primary outputs, while applying a test pattern to some device under test DUTare called the output of that test pattern. ATPG efficiency is another important consideration that is influenced by the fault model under consideration, the type of circuit under test full scansynchronous sequential, or asynchronous sequentialthe level of basicx used to represent the circuit under test gate, register-transfer, switchand the required test quality.