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I figured that if the clock was going to roll over to 00 hours, I’d need a “double” pulse to get the hours to automatically advance to 01 hours. So much for the “perfect” design that used all of the chips wisely. For the ten hours, I didn’t want to waste another 74LS and chip just to display zero and one. I had to use a very small 8-volt transformer that just barely fits inside the case to supply the low voltage power.
I experimented with using 74LS dual binary counter chips.
74LS Fairchild Semiconductor, 74LS Datasheet
One advantage to use what is essentially a binary clock with 7-segment decoders is to have small neon bulbs or LEDs driven directly from the BCD outputs. This configuration dstasheet solve the problem. The datasheet says the chip was designed to have a strong tolerance for noise, and there is no mention of this in the 74LS datasheet. I realized a design flaw when I finished the clock.
I figure since the latter was normally used in older computer systems, the power supply and datashret signals are expected to be well-filtered and free of noise. The and triggers on the rising-edge. This would’ve been a bad waste of chips, so I decided to do the remaining logics the old school way I was faced with the problem of the clock starting at 00 hours, but the clock does count nicely to 12 and resets back to The inverter using a transistor and resistor changes the “off” G into a logic 1 for the AND gate.
I originally planned on using a Mostek MK 6-digit clock chip that multiplexes the digits. I built a case out of cedar, and the amount of space I had inside the case was rather limited so I was unable to pursue my idea of using neon bulbs or LEDs for displaying the binary time directly from the 74LS counters.
I never had a problem with this in my other two clocks dstasheet run off mains, and I discovered the reason after taking a closer look at the datasheets.
I planned on placing the neon bulbs under each digit, so if you’re plain then look at the Bs and if you’re a geek then look at the binary below.
However, I had to delay the pulse from the DRL until the 10 minutes counter finished sending its clock pulse to the 1 hours counter. I used the for the first stage to divide 60Hz to 10Hz. The two diode AND gate, one connected to segment F and one to the inverted segment G, will produce a logic 1 only when segment F is on and segment G is off.
Therefore, both diodes have to have a logic 1 in order to allow the output to rise to a logic 1. There, you have it, a “double” pulse to get rid of the 00 hours.
None of the other digits have this trait. After discovering this noise problem, I swapped them around. As you can see in the schematic, the portion marked in blue uses two AND gates and one inverter gate. The 74LS clock input triggers on a falling-edge of a square wave when the square wave signal drops from a logic 1 to 0. This falling edge triggers the 74LS to advance one more time.
Anyway, on to the pictures. If you used 60Hz from mains and fed it into thethere was still some noise passing through that would make the 74LS’s go haywire. The reason is because if segment F is off or segment G is on inverter produces a logic 0then the diode s will pull down the output to ground and produce a logic 0.
I came to a point where I thought I had gotten the design, so I proceed to build the clock.
However, after trying the chip out with two nixies, I found that the brightness was not very strong. These versatile nixie tubes can allow for a variety of characters and digits with different styles.
This current draw will pull up the clock 74ls3933 of the 74LS to a logic 1 momentarily.
When the capacitor stops charging up, the 22K pull-down resistor pulls the clock input down to a logic 0. As a result, when the clock is turned on, the 1 is always on. Even a seconds display can be added to this circuit, simply add two more decoder chips on U3b and U4a. I figured that with the in the front, it would buffer out more of the noise and generate a cleaner clock datashfet for the 74LS chips. For this clock, I decided to go with the traditional 7-segment display to show the time.
Most chips come with four AND gates in one, or 6 inverters in one. A colon indicator can be added by using the 1Hz pulse off pin 5 of U3a. When the clock goes to 10, 11, or 12, the “C” is turned off so the digit 1 appears. The fundamentals of my binary clock circuitry was based on Hans Summer’s binary clock, but datasjeet operates in hour mode. The pulse goes high then low, and the falling edge triggers the 74LS Click here for the schematic diagram of the four B nixie clock.
Assembly and Testing Completed view of assembly bottom view Back to Top. After overcoming the noise problem with the 74LSs in the clock, I learned of dahasheet minor design issue. The other segments for the zero are all wired together and switched on and off by a flip-flop. I tossed this idea out and decided to drive the nixies directly, using BCD-to-7segment decoder chips.